HIP!HIP!HURRAY!!!!MY PAPER GOT SELECTED!!!!

HEY TODAY WAS NICE MY PAPER GOT SELECTED AT THE INTERNATIONAL SYMPOSIUM OF SIGITAL DESIGN AT SAN FRANSISCO!!!!!!!!!!!!!!!!!!!!!!!! THATS REALLY GREAT!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
IT WILL BE PUBLISHED AT THE IEEE JOURNAL!!!!!!!!!!EEEAHH!!!!
OK.......I'LL GIVE U THE ABSTRACT!!!
HERE IT IS:






MULTIPLEXER BASED CLB ARCHITECTURE

V.RAGHAVENDRAN
Electronics and instrumentation engineering
EEC, Chennai,
INDIA
v.raghavendran@gmail.com

Abstract


In this work, I have presented a new CLB (Configurable Logic Block) architecture that consists of only multiplexers and does not have any LUTs. This is different from the LUT (standard look-up table) based CLB architectures available in commercial FPGAs. The new function generation architecture is based on the fact that a small set of k-input Boolean functions can generate all the 22 k , k-input Boolean functions using a simple techniques using multiplexers. By using Shannon’s expansion theorem, every 16-bit function is expressed in terms of 4-bit functions that can be generated as described. The area required by the new function generation architecture is lesser than the area required by a standard 16 x 1 LUT used in commercial FPGAs. In addition, the proposed architecture consumes lesser power than the standard 16x1 LUT. None of the existing algorithms for technology mapping, packing, placement and routing have to be modified, since the new CLB architecture makes no assumptions about the set of Boolean functions to be mapped on to the FPGA. The new architecture requires a small increase in the SRAM configuration memory. This is a trivial in comparison to the reduction achieved in the area of the FPGA and power consumption, by the proposed CLB architecture.